Essay

Landscape: diagrams compiled onto computers and FPGAs

A compiler that takes a block diagram, a dataflow graph, a statechart, or a formal specification and emits CPU code, HDL, or an FPGA bitstream walks through thick prior art. This gazette maps 89 documents in six families.

Census

The job, stated plainly

A diagram (or a formal spec) is the source of truth.
An intermediate representation carries types, clocks, constraints, and partitioning.
Backends emit software, HDL, bitstreams, or mixed CPU+FPGA implementations.
Checks — probes, tests, formal verification, deadlock analysis — attach to the same spec.

LabVIEW and Simulink industrialize (1)–(3) for their own canvases. The formal-specification family industrializes (1) and (4) without requiring a vendor diagram. UML/SysML→HDL names the translation across modelling languages. Visual-programming patents cover the general diagram-to-code idea. Adjacent hardware compilation covers HLS and FPGA-as-software.

Flagship claims to read first

US4901221A
Graphical system for modelling a process and associated method
Graphical dataflow as the program.
US6219628B1
Configuring an instrument using conversion of graphical programs into hardware implementations
Graphical program converted into a hardware implementation.
EP1004085B1
Conversion of graphical programs into hardware implementations
European counterpart of the conversion thesis.
US7503027B1
Hardware description language code generation from a state diagram (related)
State diagrams compiled to HDL.
US8701081B2
Hardware-specific code generation from a graphical model
Hardware-specific code from a graphical model.
US5101491A
Synthesizing, generating and checking software from a formal description
Software from a formal description.
US10572618B2
Processing a formal specification of a digital circuit
Formal specification of a digital circuit, processed.
WO2008075087A1
Automatically translating modelling-language code to hardware-language code
Modelling language automatically translated to hardware language.
US6230307B1
Programming FPGAs and related reconfiguration resources as if they were software
FPGAs programmed as if they were software.
US9983852B2
Graphical specification and constraint language for developing programs for hardware implementation
Graphical specification and constraint language for hardware.

What this atlas is not

It is not a freedom-to-operate opinion, a claim chart, or legal advice. It is a public, citable map of published documents so that engineers, examiners, and agents can find the neighborhood. Patent texts remain with their issuing offices; Google Patents links go to the primary record.

LabVIEW. The densest cluster: virtual instruments as dataflow graphs, then conversion of those graphs into hardware descriptions, probes, resource estimates, and multi-model-of-computation programs.

Simulink. Model-based design: block diagrams and state machines compiled to C, HDL, and partitioned targets, with a heavy test-generation and verification overlay.

Formal spec. A separate lineage: write a formal (or semi-formal) specification, then synthesize software, UIs, or digital-circuit implementations, often with checking against the spec.

UML → HDL. A thin but distinct bridge: modelling-language code (UML/SysML-class) automatically translated into hardware-language code.

Visual programming. Block-diagram simulators, immersive visual programming, evented dataflow, converting visual diagrams into code, signal-processing pipelines, and safety-critical model-based processes.

Hardware compilation. Not always a diagram: C-class hardware designs compiled to gates, FPGAs programmed as if they were software, and deadlock analysis in formally verified circuits.