Various
UML/SysML to HDL
Systems modeling languages lowered to hardware description
WO2008075087A1 is the explicit “modelling language → hardware language” publication in this atlas. It matters because it names the translation itself, not a particular vendor’s canvas.
UML, SysML, and related MBSE notations are diagrams with semantics. Compiling those semantics to VHDL/Verilog is the same job LabVIEW FPGA and Simulink HDL Coder perform for their own notations. Treat this as a sibling claim, not a curiosity.