Families

Graphical dataflow → CPU, FPGA, and mixed targets

The densest cluster: virtual instruments as dataflow graphs, then conversion of those graphs into hardware descriptions, probes, resource estimates, and multi-model-of-computation programs.

Block diagrams and statecharts → embedded code and HDL

Model-based design: block diagrams and state machines compiled to C, HDL, and partitioned targets, with a heavy test-generation and verification overlay.

Formal descriptions → verified software and circuits

A separate lineage: write a formal (or semi-formal) specification, then synthesize software, UIs, or digital-circuit implementations, often with checking against the spec.

Systems modeling languages lowered to hardware description

A thin but distinct bridge: modelling-language code (UML/SysML-class) automatically translated into hardware-language code.

Diagrams, dataflow, and visual specs outside the two vendor stacks

Block-diagram simulators, immersive visual programming, evented dataflow, converting visual diagrams into code, signal-processing pipelines, and safety-critical model-based processes.

High-level programs and FPGA-as-software, plus formal hardware checks

Not always a diagram: C-class hardware designs compiled to gates, FPGAs programmed as if they were software, and deadlock analysis in formally verified circuits.