National Instruments
National Instruments / LabVIEW
Graphical dataflow → CPU, FPGA, and mixed targets
LabVIEW is the longest-running commercial proof that a diagram can be the program. The 1990 Kodosky patent (US4901221) treats a block diagram as an executable dataflow specification. Later members of the family stop treating the diagram as a UI over software and start treating it as a specification that can be compiled onto programmable hardware.
The conversion patents (US6219628 and its continuations) are the core “graphical program → FPGA / HDL” claims. Around them sit resource estimation, probe insertion for hardware debug, targeting portions of one diagram at CPU and FPGA together, nested models of computation, and a graphical specification-and-constraint language aimed at hardware implementation.
For anyone compiling diagrams onto computers or FPGAs, this is the thicket. The claims are not “a box that draws boxes.” They are methods for representing a graphical program, lowering it, partitioning it, and emitting a hardware description or a mixed software/hardware implementation.
Members (32)
- US4901221A1990grantedGraphical system for modelling a process and associated method
- US5301336A1994grantedGraphical method for programming a virtual instrument
- US5481741A1996grantedMethod and apparatus for providing attribute nodes in a graphical data flow environment
- US6219628B12001grantedConfiguring an instrument using conversion of graphical programs into hardware implementations
- EP1004085B12003grantedConversion of graphical programs into hardware implementations
- US6584601B12003grantedConverting graphical programs into hardware implementations which utilize probe insertion
- US6608638B12003grantedConfiguring a programmable hardware instrument; estimation of hardware implementation and resource management
- US6784903B22004grantedConfiguring an instrument using conversion of graphical programs into hardware implementations
- US6934668B22005grantedSpecifying and targeting portions of a graphical program for execution by multiple targets
- US20070225954A12007applicationImplementing a graphical program on a programmable hardware element to configure an instrument
- US7177786B22007grantedSpecifying and targeting portions of a graphical program for execution by multiple targets
- US7210117B22007grantedProgrammatically generating a graphical program in response to program information
- US7530052B22009grantedCreating and executing a graphical program with a first model of computation that includes a structure supporting a second
- US7558711B22009grantedGenerating a hardware description of a block diagram model for implementation on programmable hardware
- US20100057417A12010applicationHardware description from a graphical program including multiple physical domains
- US20100058289A12010applicationHardware description from a graphical program including multiple models of computation
- US7707014B22010grantedImplementing a data flow block diagram having a control flow node on a programmable hardware element
- US7743362B22010grantedAutomatic generation of application-domain-specific graphical programs
- US7836426B22010grantedAutomatic generation of application-domain-specific graphical programs
- US8146053B22012grantedGraphical programming environment with first model of computation supporting a second
- WO2012015496A12012applicationSpecification of isochronous data transfer in a graphical programming language
- WO2012016078A12012applicationDeveloping programs in a graphical specification and constraint language
- US8397214B22013grantedHardware description from a graphical program including multiple physical domains
- US8453111B22013grantedHardware description from a graphical program including multiple models of computation
- US8458653B22013grantedDebugging a graphical program deployed on a programmable hardware element
- US8479156B22013grantedProviding target-specific information for textual code at edit time
- US8516436B22013grantedEncapsulating a graphical program within a standard image file
- US20150242193A12015applicationProgram optimization via compile-time execution
- US8935661B22015grantedHardware description from a graphical program including multiple models of computation
- US9135143B22015grantedAutomated analysis of compilation processes in a graphical specification and constraint language
- US9904523B22018grantedGraphical development and deployment of parallel floating-point math on heterogeneous hardware
- US9983852B22018grantedGraphical specification and constraint language for developing programs for hardware implementation