MathWorks
MathWorks / Simulink
Block diagrams and statecharts → embedded code and HDL
Simulink and Stateflow are the other industrial diagram-as-spec stack. Where LabVIEW leans dataflow and virtual instruments, this family leans control systems, discrete/continuous time, and statecharts (Moore/Mealy restrictions, event aggregation, parallel vs sequential implementations).
Code generation is first-class: HDL from state diagrams, hardware-specific code from a graphical model, intermediate representations used to verify generated code, and compilation of whole system designs. A parallel line of patents covers automated test generation from pre- and post-conditions on the model.
The recent publications (source code from a block diagram; code generation from a control model) show the same thesis still being filed: the diagram is the source of truth; the compiler’s job is to emit software, HDL, or both.
Members (19)
- US7503027B12009grantedHardware description language code generation from a state diagram (related)
- US7680632B12010grantedTest precondition items for automated analysis and test generation
- US7729894B12010grantedTest postcondition items for automated analysis and test generation
- US7752559B12010grantedGraphical model preparation for embedded deployment
- US7840913B12010grantedRestricting state diagrams to Moore/Mealy machines
- US7865350B12010grantedPartitioning a model in modeling environments
- US7974823B12011grantedTest postcondition items for automated analysis and test generation
- US20120005650A12012applicationHardware-specific code generation
- US8141011B12012grantedHardware description language code generation from a state diagram
- US8701081B22014grantedHardware-specific code generation from a graphical model
- US8869103B22014grantedUsing intermediate representations to verify computer-executable code generated from a model
- US8903688B12014grantedTest entities for evaluation and validation of a model
- US8984496B22014grantedExtensible internal representation of systems with parallel and sequential implementations
- WO2014209432A12014applicationCompilation of system designs
- US9880922B12018grantedAutomatically generating a graphical model from a text-based program; HDL and synthesis
- US10706193B12020grantedComputer processing during simulation of a circuit design
- US11327725B22022grantedAggregating implicit and explicit event code of executable models
- US20250165232A12025applicationMethod for generating source code from a block diagram
- WO2025182189A12025applicationCode generation device, system, and method from a control model