Gazette entry
US8869103B2
Using intermediate representations to verify computer-executable code generated from a model
Intermediate representations used to verify executable code generated from a model.
- Family
- Block diagrams and statecharts → embedded code and HDL
- Tags
- simulink · codegen · verify
How to cite
US8869103B2, “Using intermediate representations to verify computer-executable code generated from a model,” MathWorks / Simulink, 2014.
Same family
- US7503027B1Hardware description language code generation from a state diagram (related)
- US7680632B1Test precondition items for automated analysis and test generation
- US7729894B1Test postcondition items for automated analysis and test generation
- US7752559B1Graphical model preparation for embedded deployment
- US7840913B1Restricting state diagrams to Moore/Mealy machines
- US7865350B1Partitioning a model in modeling environments