Various
Adjacent hardware compilation
High-level programs and FPGA-as-software, plus formal hardware checks
Three patents sit next to the diagram compilers rather than inside them.
US6226776B1 is the high-level-language-to-hardware implementation claim — the HLS neighbor of “diagram to HDL.” US6230307B1 is the FPGA-as-software claim: reconfiguration resources programmed with a software mindset. US11580284B1 is formal verification of circuits, specifically deadlock, which a serious diagram-to-FPGA compiler with formal specs will eventually touch.
Together they close the loop: a graphical or textual spec, a compiler onto programmable hardware, and a checker for the resulting circuit.
Members (3)
- US6226776B12001grantedConverting hardware designs in a high-level programming language to hardware implementations
- US6230307B12001grantedProgramming FPGAs and related reconfiguration resources as if they were software
- US11580284B12023grantedFinding and analyzing deadlock conditions associated with formal verification of an electronic circuit design