Gazette entry

US11580284B1

Finding and analyzing deadlock conditions associated with formal verification of an electronic circuit design

Deadlock conditions found and analyzed during formal verification of a circuit design.

Family

High-level programs and FPGA-as-software, plus formal hardware checks

Tags

hardware · formal · verify

US11580284B1, “Finding and analyzing deadlock conditions associated with formal verification of an electronic circuit design,” Adjacent hardware compilation, 2023.