# US11580284B1

**Finding and analyzing deadlock conditions associated with formal verification of an electronic circuit design**

- Year: 2023
- Kind: granted
- Family: [Adjacent hardware compilation](https://lattice-gazette.pages.dev/families/hardware.md)
- Tags: hardware, formal, verify
- Google Patents: https://patents.google.com/patent/US11580284B1

Deadlock conditions found and analyzed during formal verification of a circuit design.

## Citation

`US11580284B1, "Finding and analyzing deadlock conditions associated with formal verification of an electronic circuit design," Adjacent hardware compilation, 2023. Indexed at Lattice Gazette.`

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