# Lattice Gazette — full corpus

> A public, agent-readable atlas of patents covering graphical programs, formal specifications, and the compilers that lower them onto CPUs and programmable hardware.
> Source: https://lattice-gazette.pages.dev/
> Patents: 89

# Landscape: diagrams compiled onto computers and FPGAs

A compiler that takes a block diagram, a dataflow graph, a statechart, or a formal specification and emits CPU code, HDL, or an FPGA bitstream walks through thick prior art. This gazette maps 89 documents in six families.

## Census

- **LabVIEW**: 32 documents
- **Simulink**: 19 documents
- **Formal spec**: 19 documents
- **UML → HDL**: 1 documents
- **Visual programming**: 15 documents
- **Hardware compilation**: 3 documents

## The job, stated plainly

1. A **diagram** (or a formal spec) is the source of truth.
2. An **intermediate representation** carries types, clocks, constraints, and partitioning.
3. **Backends** emit software, HDL, bitstreams, or mixed CPU+FPGA implementations.
4. **Checks** — probes, tests, formal verification, deadlock analysis — attach to the same spec.

LabVIEW and Simulink industrialize (1)–(3) for their own canvases. The formal-specification family industrializes (1) and (4) without requiring a vendor diagram. UML/SysML→HDL names the translation across modelling languages. Visual-programming patents cover the general diagram-to-code idea. Adjacent hardware compilation covers HLS and FPGA-as-software.

## Flagship claims to read first

- **US4901221A** (1990) — graphical dataflow as the program.
- **US6219628B1** (2001) — graphical program converted into a hardware implementation.
- **EP1004085B1** — European counterpart of the conversion thesis.
- **US7503027B1 / US8141011B1** — state diagrams to HDL.
- **US8701081B2** — hardware-specific code from a graphical model.
- **US5101491A** — software from a formal description.
- **US10572618B2** — processing a formal specification of a digital circuit.
- **WO2008075087A1** — modelling language to hardware language.
- **US6230307B1** — programming FPGAs as if they were software.
- **US9983852B2** — graphical specification and constraint language for hardware.

## What this atlas is not

It is not a freedom-to-operate opinion, a claim chart, or legal advice. It is a public, citable map of published documents so that engineers, examiners, and agents can find the neighborhood.


---

## National Instruments / LabVIEW

LabVIEW is the longest-running commercial proof that a diagram can be the program. The 1990 Kodosky patent (US4901221) treats a block diagram as an executable dataflow specification. Later members of the family stop treating the diagram as a UI over software and start treating it as a specification that can be compiled onto programmable hardware.

The conversion patents (US6219628 and its continuations) are the core “graphical program → FPGA / HDL” claims. Around them sit resource estimation, probe insertion for hardware debug, targeting portions of one diagram at CPU and FPGA together, nested models of computation, and a graphical specification-and-constraint language aimed at hardware implementation.

For anyone compiling diagrams onto computers or FPGAs, this is the thicket. The claims are not “a box that draws boxes.” They are methods for representing a graphical program, lowering it, partitioning it, and emitting a hardware description or a mixed software/hardware implementation.

### US4901221A (1990, granted)
**Graphical system for modelling a process and associated method**
- Family: National Instruments / LabVIEW
- Tags: labview, compilation
- Foundational LabVIEW grant: a graphical dataflow diagram is the program, not a drawing of one.
- Page: /patents/US4901221A
- Google Patents: https://patents.google.com/patent/US4901221A

### US5301336A (1994, granted)
**Graphical method for programming a virtual instrument**
- Family: National Instruments / LabVIEW
- Tags: labview, compilation
- Virtual instruments programmed as graphical block diagrams — the VI as an executable spec.
- Page: /patents/US5301336A
- Google Patents: https://patents.google.com/patent/US5301336A

### US5481741A (1996, granted)
**Method and apparatus for providing attribute nodes in a graphical data flow environment**
- Family: National Instruments / LabVIEW
- Tags: labview, dataflow
- Method and apparatus for providing attribute nodes in a graphical data flow environment. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US5481741A
- Google Patents: https://patents.google.com/patent/US5481741A

### US6219628B1 (2001, granted)
**Configuring an instrument using conversion of graphical programs into hardware implementations**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- The conversion patent: a graphical program is compiled into a hardware implementation that configures an instrument.
- Page: /patents/US6219628B1
- Google Patents: https://patents.google.com/patent/US6219628B1

### EP1004085B1 (2003, granted)
**Conversion of graphical programs into hardware implementations**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Conversion of graphical programs into hardware implementations. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/EP1004085B1
- Google Patents: https://patents.google.com/patent/EP1004085B1

### US6584601B1 (2003, granted)
**Converting graphical programs into hardware implementations which utilize probe insertion**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, debug
- Same conversion path, with probe insertion so the hardware implementation can be observed.
- Page: /patents/US6584601B1
- Google Patents: https://patents.google.com/patent/US6584601B1

### US6608638B1 (2003, granted)
**Configuring a programmable hardware instrument; estimation of hardware implementation and resource management**
- Family: National Instruments / LabVIEW
- Tags: labview, fpga
- Resource estimation and management when a graphical program is lowered onto programmable hardware.
- Page: /patents/US6608638B1
- Google Patents: https://patents.google.com/patent/US6608638B1

### US6784903B2 (2004, granted)
**Configuring an instrument using conversion of graphical programs into hardware implementations**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Configuring an instrument using conversion of graphical programs into hardware implementations. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US6784903B2
- Google Patents: https://patents.google.com/patent/US6784903B2

### US6934668B2 (2005, granted)
**Specifying and targeting portions of a graphical program for execution by multiple targets**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, multi-target
- One graphical program, multiple targets — portions specified for CPU, FPGA, or other executors.
- Page: /patents/US6934668B2
- Google Patents: https://patents.google.com/patent/US6934668B2

### US20070225954A1 (2007, application)
**Implementing a graphical program on a programmable hardware element to configure an instrument**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Implementing a graphical program on a programmable hardware element to configure an instrument. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US20070225954A1
- Google Patents: https://patents.google.com/patent/US20070225954A1

### US7177786B2 (2007, granted)
**Specifying and targeting portions of a graphical program for execution by multiple targets**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, multi-target
- Specifying and targeting portions of a graphical program for execution by multiple targets. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US7177786B2
- Google Patents: https://patents.google.com/patent/US7177786B2

### US7210117B2 (2007, granted)
**Programmatically generating a graphical program in response to program information**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram
- Programmatically generating a graphical program in response to program information. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US7210117B2
- Google Patents: https://patents.google.com/patent/US7210117B2

### US7530052B2 (2009, granted)
**Creating and executing a graphical program with a first model of computation that includes a structure supporting a second**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, moc
- Nested models of computation: a graphical program whose structures host a second MoC.
- Page: /patents/US7530052B2
- Google Patents: https://patents.google.com/patent/US7530052B2

### US7558711B2 (2009, granted)
**Generating a hardware description of a block diagram model for implementation on programmable hardware**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Block-diagram model in, hardware description out, for implementation on programmable hardware.
- Page: /patents/US7558711B2
- Google Patents: https://patents.google.com/patent/US7558711B2

### US20100057417A1 (2010, application)
**Hardware description from a graphical program including multiple physical domains**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Hardware description from a graphical program including multiple physical domains. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US20100057417A1
- Google Patents: https://patents.google.com/patent/US20100057417A1

### US20100058289A1 (2010, application)
**Hardware description from a graphical program including multiple models of computation**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, moc
- Hardware description from a graphical program including multiple models of computation. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US20100058289A1
- Google Patents: https://patents.google.com/patent/US20100058289A1

### US7707014B2 (2010, granted)
**Implementing a data flow block diagram having a control flow node on a programmable hardware element**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, dataflow
- Implementing a data flow block diagram having a control flow node on a programmable hardware element. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US7707014B2
- Google Patents: https://patents.google.com/patent/US7707014B2

### US7743362B2 (2010, granted)
**Automatic generation of application-domain-specific graphical programs**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram
- Automatic generation of application-domain-specific graphical programs. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US7743362B2
- Google Patents: https://patents.google.com/patent/US7743362B2

### US7836426B2 (2010, granted)
**Automatic generation of application-domain-specific graphical programs**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram
- Automatic generation of application-domain-specific graphical programs. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US7836426B2
- Google Patents: https://patents.google.com/patent/US7836426B2

### US8146053B2 (2012, granted)
**Graphical programming environment with first model of computation supporting a second**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, moc
- Graphical programming environment with first model of computation supporting a second. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8146053B2
- Google Patents: https://patents.google.com/patent/US8146053B2

### WO2012015496A1 (2012, application)
**Specification of isochronous data transfer in a graphical programming language**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, formal
- Specification of isochronous data transfer in a graphical programming language. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/WO2012015496A1
- Google Patents: https://patents.google.com/patent/WO2012015496A1

### WO2012016078A1 (2012, application)
**Developing programs in a graphical specification and constraint language**
- Family: National Instruments / LabVIEW
- Tags: labview, formal
- Developing programs in a graphical specification and constraint language. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/WO2012016078A1
- Google Patents: https://patents.google.com/patent/WO2012016078A1

### US8397214B2 (2013, granted)
**Hardware description from a graphical program including multiple physical domains**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga
- Hardware description from a graphical program including multiple physical domains. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8397214B2
- Google Patents: https://patents.google.com/patent/US8397214B2

### US8453111B2 (2013, granted)
**Hardware description from a graphical program including multiple models of computation**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, moc
- Hardware description from a graphical program including multiple models of computation. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8453111B2
- Google Patents: https://patents.google.com/patent/US8453111B2

### US8458653B2 (2013, granted)
**Debugging a graphical program deployed on a programmable hardware element**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, debug
- Debugging a graphical program after it has been deployed onto a programmable hardware element.
- Page: /patents/US8458653B2
- Google Patents: https://patents.google.com/patent/US8458653B2

### US8479156B2 (2013, granted)
**Providing target-specific information for textual code at edit time**
- Family: National Instruments / LabVIEW
- Tags: labview, compilation
- Providing target-specific information for textual code at edit time. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8479156B2
- Google Patents: https://patents.google.com/patent/US8479156B2

### US8516436B2 (2013, granted)
**Encapsulating a graphical program within a standard image file**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram
- Encapsulating a graphical program within a standard image file. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8516436B2
- Google Patents: https://patents.google.com/patent/US8516436B2

### US20150242193A1 (2015, application)
**Program optimization via compile-time execution**
- Family: National Instruments / LabVIEW
- Tags: labview, compilation
- Program optimization via compile-time execution. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US20150242193A1
- Google Patents: https://patents.google.com/patent/US20150242193A1

### US8935661B2 (2015, granted)
**Hardware description from a graphical program including multiple models of computation**
- Family: National Instruments / LabVIEW
- Tags: labview, diagram, fpga, moc
- Hardware description from a graphical program including multiple models of computation. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US8935661B2
- Google Patents: https://patents.google.com/patent/US8935661B2

### US9135143B2 (2015, granted)
**Automated analysis of compilation processes in a graphical specification and constraint language**
- Family: National Instruments / LabVIEW
- Tags: labview, formal
- Automated analysis of compilation processes in a graphical specification and constraint language. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US9135143B2
- Google Patents: https://patents.google.com/patent/US9135143B2

### US9904523B2 (2018, granted)
**Graphical development and deployment of parallel floating-point math on heterogeneous hardware**
- Family: National Instruments / LabVIEW
- Tags: labview, fpga, multi-target
- Graphical development and deployment of parallel floating-point math on heterogeneous hardware. Filed in the National Instruments / LabVIEW cluster.
- Page: /patents/US9904523B2
- Google Patents: https://patents.google.com/patent/US9904523B2

### US9983852B2 (2018, granted)
**Graphical specification and constraint language for developing programs for hardware implementation**
- Family: National Instruments / LabVIEW
- Tags: labview, fpga, formal
- A graphical specification and constraint language whose programs are intended for hardware implementation.
- Page: /patents/US9983852B2
- Google Patents: https://patents.google.com/patent/US9983852B2

---

## MathWorks / Simulink

Simulink and Stateflow are the other industrial diagram-as-spec stack. Where LabVIEW leans dataflow and virtual instruments, this family leans control systems, discrete/continuous time, and statecharts (Moore/Mealy restrictions, event aggregation, parallel vs sequential implementations).

Code generation is first-class: HDL from state diagrams, hardware-specific code from a graphical model, intermediate representations used to verify generated code, and compilation of whole system designs. A parallel line of patents covers automated test generation from pre- and post-conditions on the model.

The recent publications (source code from a block diagram; code generation from a control model) show the same thesis still being filed: the diagram is the source of truth; the compiler’s job is to emit software, HDL, or both.

### US7503027B1 (2009, granted)
**Hardware description language code generation from a state diagram (related)**
- Family: MathWorks / Simulink
- Tags: simulink, fpga, statechart, codegen
- State diagram (Stateflow-class) compiled to a hardware description language.
- Page: /patents/US7503027B1
- Google Patents: https://patents.google.com/patent/US7503027B1

### US7680632B1 (2010, granted)
**Test precondition items for automated analysis and test generation**
- Family: MathWorks / Simulink
- Tags: simulink, test
- Test precondition items for automated analysis and test generation. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7680632B1
- Google Patents: https://patents.google.com/patent/US7680632B1

### US7729894B1 (2010, granted)
**Test postcondition items for automated analysis and test generation**
- Family: MathWorks / Simulink
- Tags: simulink, test
- Test postcondition items for automated analysis and test generation. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7729894B1
- Google Patents: https://patents.google.com/patent/US7729894B1

### US7752559B1 (2010, granted)
**Graphical model preparation for embedded deployment**
- Family: MathWorks / Simulink
- Tags: simulink, compilation
- Graphical model preparation for embedded deployment. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7752559B1
- Google Patents: https://patents.google.com/patent/US7752559B1

### US7840913B1 (2010, granted)
**Restricting state diagrams to Moore/Mealy machines**
- Family: MathWorks / Simulink
- Tags: simulink, statechart
- Restricting state diagrams to Moore/Mealy machines. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7840913B1
- Google Patents: https://patents.google.com/patent/US7840913B1

### US7865350B1 (2010, granted)
**Partitioning a model in modeling environments**
- Family: MathWorks / Simulink
- Tags: simulink, multi-target
- Partitioning a model in modeling environments. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7865350B1
- Google Patents: https://patents.google.com/patent/US7865350B1

### US7974823B1 (2011, granted)
**Test postcondition items for automated analysis and test generation**
- Family: MathWorks / Simulink
- Tags: simulink, test
- Test postcondition items for automated analysis and test generation. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US7974823B1
- Google Patents: https://patents.google.com/patent/US7974823B1

### US20120005650A1 (2012, application)
**Hardware-specific code generation**
- Family: MathWorks / Simulink
- Tags: simulink, fpga, codegen
- Hardware-specific code generation. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US20120005650A1
- Google Patents: https://patents.google.com/patent/US20120005650A1

### US8141011B1 (2012, granted)
**Hardware description language code generation from a state diagram**
- Family: MathWorks / Simulink
- Tags: simulink, fpga, statechart, codegen
- Hardware description language code generation from a state diagram. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US8141011B1
- Google Patents: https://patents.google.com/patent/US8141011B1

### US8701081B2 (2014, granted)
**Hardware-specific code generation from a graphical model**
- Family: MathWorks / Simulink
- Tags: simulink, fpga, codegen
- Hardware-specific code generation from a graphical model — Simulink’s HLS-adjacent grant.
- Page: /patents/US8701081B2
- Google Patents: https://patents.google.com/patent/US8701081B2

### US8869103B2 (2014, granted)
**Using intermediate representations to verify computer-executable code generated from a model**
- Family: MathWorks / Simulink
- Tags: simulink, codegen, verify
- Intermediate representations used to verify executable code generated from a model.
- Page: /patents/US8869103B2
- Google Patents: https://patents.google.com/patent/US8869103B2

### US8903688B1 (2014, granted)
**Test entities for evaluation and validation of a model**
- Family: MathWorks / Simulink
- Tags: simulink, test
- Test entities for evaluation and validation of a model. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US8903688B1
- Google Patents: https://patents.google.com/patent/US8903688B1

### US8984496B2 (2014, granted)
**Extensible internal representation of systems with parallel and sequential implementations**
- Family: MathWorks / Simulink
- Tags: simulink, compilation
- Extensible internal representation of systems with parallel and sequential implementations. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US8984496B2
- Google Patents: https://patents.google.com/patent/US8984496B2

### WO2014209432A1 (2014, application)
**Compilation of system designs**
- Family: MathWorks / Simulink
- Tags: simulink, compilation
- Compilation of system designs. Filed in the MathWorks / Simulink cluster.
- Page: /patents/WO2014209432A1
- Google Patents: https://patents.google.com/patent/WO2014209432A1

### US9880922B1 (2018, granted)
**Automatically generating a graphical model from a text-based program; HDL and synthesis**
- Family: MathWorks / Simulink
- Tags: simulink, fpga
- The reverse compiler: text program to graphical model, including HDL and synthesis.
- Page: /patents/US9880922B1
- Google Patents: https://patents.google.com/patent/US9880922B1

### US10706193B1 (2020, granted)
**Computer processing during simulation of a circuit design**
- Family: MathWorks / Simulink
- Tags: simulink, compilation
- Computer processing during simulation of a circuit design. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US10706193B1
- Google Patents: https://patents.google.com/patent/US10706193B1

### US11327725B2 (2022, granted)
**Aggregating implicit and explicit event code of executable models**
- Family: MathWorks / Simulink
- Tags: simulink, codegen
- Aggregating implicit and explicit event code of executable models. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US11327725B2
- Google Patents: https://patents.google.com/patent/US11327725B2

### US20250165232A1 (2025, application)
**Method for generating source code from a block diagram**
- Family: MathWorks / Simulink
- Tags: simulink, diagram, codegen
- Method for generating source code from a block diagram. Filed in the MathWorks / Simulink cluster.
- Page: /patents/US20250165232A1
- Google Patents: https://patents.google.com/patent/US20250165232A1

### WO2025182189A1 (2025, application)
**Code generation device, system, and method from a control model**
- Family: MathWorks / Simulink
- Tags: simulink, codegen
- Code generation device, system, and method from a control model. Filed in the MathWorks / Simulink cluster.
- Page: /patents/WO2025182189A1
- Google Patents: https://patents.google.com/patent/WO2025182189A1

---

## Formal specification to code

This family is not a graphical language, but it is the other half of “diagrams into executable specifications.” A formal description — algebraic, model-based, or a software-spec modeling language — is compiled into source, executables, or circuit processing pipelines.

US5101491 (1992) is an early “synthesize, generate and check software from a formal description.” The Automatic Software Production cluster (US7278130 and continuations) industrializes model-driven generation of information systems and UIs. Later grants cover analytical software design, pattern matching in procedure verification, and processing a formal specification of a digital circuit.

The Chinese grant CN112306470B sits at the synchronous-language end: transform and automatically verify complex synchronous programs — the same intellectual neighborhood as Lustre/SCADE, which themselves compile diagrams and equations onto embedded targets.

A compiler that takes a diagram plus a formal spec and emits proven CPU or FPGA code inherits prior art from both this stack and the LabVIEW/Simulink stacks.

### US5101491A (1992, granted)
**Synthesizing, generating and checking software from a formal description**
- Family: Formal specification to code
- Tags: formal-spec, formal, verify
- Early formal-methods compiler: synthesize, generate, and check software from a formal description.
- Page: /patents/US5101491A
- Google Patents: https://patents.google.com/patent/US5101491A

### US7278130B2 (2007, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production from models — industrial model-driven generation of systems.
- Page: /patents/US7278130B2
- Google Patents: https://patents.google.com/patent/US7278130B2

### US7334216B2 (2008, granted)
**Automatic generation of information-system user interfaces**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic generation of information-system user interfaces. Filed in the Formal specification to code cluster.
- Page: /patents/US7334216B2
- Google Patents: https://patents.google.com/patent/US7334216B2

### US7555742B2 (2009, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US7555742B2
- Google Patents: https://patents.google.com/patent/US7555742B2

### US7584451B2 (2009, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US7584451B2
- Google Patents: https://patents.google.com/patent/US7584451B2

### US7739671B1 (2010, granted)
**Implementation of formal specifications derived from informal requirements**
- Family: Formal specification to code
- Tags: formal-spec, formal
- Implementation of formal specifications derived from informal requirements. Filed in the Formal specification to code cluster.
- Page: /patents/US7739671B1
- Google Patents: https://patents.google.com/patent/US7739671B1

### US7941438B2 (2011, granted)
**Automatic generation of information-system user interfaces**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic generation of information-system user interfaces. Filed in the Formal specification to code cluster.
- Page: /patents/US7941438B2
- Google Patents: https://patents.google.com/patent/US7941438B2

### US7979848B2 (2011, granted)
**Pattern matching in procedure development and verification**
- Family: Formal specification to code
- Tags: formal-spec, verify
- Pattern matching in procedure development and verification. Filed in the Formal specification to code cluster.
- Page: /patents/US7979848B2
- Google Patents: https://patents.google.com/patent/US7979848B2

### US8037449B2 (2011, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US8037449B2
- Google Patents: https://patents.google.com/patent/US8037449B2

### US8141031B2 (2012, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US8141031B2
- Google Patents: https://patents.google.com/patent/US8141031B2

### US8245183B2 (2012, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US8245183B2
- Google Patents: https://patents.google.com/patent/US8245183B2

### US8365138B2 (2013, granted)
**Automatic software production system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Automatic software production system. Filed in the Formal specification to code cluster.
- Page: /patents/US8365138B2
- Google Patents: https://patents.google.com/patent/US8365138B2

### US8370798B2 (2013, granted)
**Analytical software design system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Analytical software design system. Filed in the Formal specification to code cluster.
- Page: /patents/US8370798B2
- Google Patents: https://patents.google.com/patent/US8370798B2

### US8943465B2 (2015, granted)
**Analytical software design system**
- Family: Formal specification to code
- Tags: formal-spec, compilation
- Analytical software design system. Filed in the Formal specification to code cluster.
- Page: /patents/US8943465B2
- Google Patents: https://patents.google.com/patent/US8943465B2

### US9038036B2 (2015, granted)
**Generation of source code and executable code from formal descriptions**
- Family: Formal specification to code
- Tags: formal-spec, formal, codegen
- Source and executable code generated from formal descriptions.
- Page: /patents/US9038036B2
- Google Patents: https://patents.google.com/patent/US9038036B2

### US20160170714A1 (2016, application)
**Method and system of software specification modeling**
- Family: Formal specification to code
- Tags: formal-spec, formal
- Method and system of software specification modeling. Filed in the Formal specification to code cluster.
- Page: /patents/US20160170714A1
- Google Patents: https://patents.google.com/patent/US20160170714A1

### US10409563B2 (2019, granted)
**Generating application code from a formal specification**
- Family: Formal specification to code
- Tags: formal-spec, formal
- Generating application code from a formal specification. Filed in the Formal specification to code cluster.
- Page: /patents/US10409563B2
- Google Patents: https://patents.google.com/patent/US10409563B2

### US10572618B2 (2020, granted)
**Processing a formal specification of a digital circuit**
- Family: Formal specification to code
- Tags: formal-spec, formal
- A formal specification of a digital circuit, processed toward an implementation.
- Page: /patents/US10572618B2
- Google Patents: https://patents.google.com/patent/US10572618B2

### CN112306470B (2021, granted)
**Simplified transformation and automatic verification of complex synchronous-language programs**
- Family: Formal specification to code
- Tags: formal-spec, verify
- Simplified transformation and automatic verification of complex synchronous-language programs. Filed in the Formal specification to code cluster.
- Page: /patents/CN112306470B
- Google Patents: https://patents.google.com/patent/CN112306470B

---

## UML/SysML to HDL

WO2008075087A1 is the explicit “modelling language → hardware language” publication in this atlas. It matters because it names the translation itself, not a particular vendor’s canvas.

UML, SysML, and related MBSE notations are diagrams with semantics. Compiling those semantics to VHDL/Verilog is the same job LabVIEW FPGA and Simulink HDL Coder perform for their own notations. Treat this as a sibling claim, not a curiosity.

### WO2008075087A1 (2008, application)
**Automatically translating modelling-language code to hardware-language code**
- Family: UML/SysML to HDL
- Tags: uml-hdl, fpga
- Modelling-language code automatically translated into hardware-language code.
- Page: /patents/WO2008075087A1
- Google Patents: https://patents.google.com/patent/WO2008075087A1

---

## Other graphical / visual programming

Before and beside LabVIEW and Simulink, a wide field treated diagrams as programs: real-time multirate code generators, workstations for graphic representations of programs, library-driven block-diagram simulators, immersive visual programming, and evented dataflow.

The 2018-era grants (converting visual diagrams into code; graphical programming with simulation; formal specs from examples; safety-critical model-based development) show the idea never left. If a product draws a graph and emits an executable, these are the non-NI, non-MathWorks neighbors.

US10331415B2 (formal specification generation using examples) is a useful hinge: it sits in “visual programming” but points at the formal-spec family — examples in, spec out, then code.

### US4796179A (1989, granted)
**Multirate real-time control system code generator**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Multirate real-time control system code generator. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US4796179A
- Google Patents: https://patents.google.com/patent/US4796179A

### US4831580A (1989, granted)
**Program generator**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Program generator. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US4831580A
- Google Patents: https://patents.google.com/patent/US4831580A

### US4860204A (1989, granted)
**Workstation for development of graphic representations of computer programs**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Workstation for development of graphic representations of computer programs. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US4860204A
- Google Patents: https://patents.google.com/patent/US4860204A

### US5151984A (1992, granted)
**Block-diagram simulator using a library for generation of a computer program**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Block-diagram simulator using a library for generation of a computer program. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US5151984A
- Google Patents: https://patents.google.com/patent/US5151984A

### US5758122A (1998, granted)
**Immersive visual programming system**
- Family: Other graphical / visual programming
- Tags: visual, diagram
- Immersive visual programming system. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US5758122A
- Google Patents: https://patents.google.com/patent/US5758122A

### US6272672B1 (2001, granted)
**Dataflow processing with events**
- Family: Other graphical / visual programming
- Tags: visual, dataflow
- Dataflow processing with events. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US6272672B1
- Google Patents: https://patents.google.com/patent/US6272672B1

### US6366300B1 (2002, granted)
**Visual programming method and system**
- Family: Other graphical / visual programming
- Tags: visual, diagram
- Visual programming method and system. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US6366300B1
- Google Patents: https://patents.google.com/patent/US6366300B1

### US7853937B2 (2010, granted)
**Object-oriented parallel language / multi-processor computer**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Object-oriented parallel language / multi-processor computer. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US7853937B2
- Google Patents: https://patents.google.com/patent/US7853937B2

### US10048946B2 (2018, granted)
**Converting visual diagrams into code**
- Family: Other graphical / visual programming
- Tags: visual, diagram
- Visual diagrams converted into code — the general (non-vendor) diagram-to-program claim.
- Page: /patents/US10048946B2
- Google Patents: https://patents.google.com/patent/US10048946B2

### US10089081B2 (2018, granted)
**Method and/or apparatus for generating signal processing pipelines**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Method and/or apparatus for generating signal processing pipelines. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US10089081B2
- Google Patents: https://patents.google.com/patent/US10089081B2

### US10209963B2 (2019, granted)
**Parallelization of program code, interactive data visualization, and graphically-augmented code editing**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Parallelization of program code, interactive data visualization, and graphically-augmented code editing. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US10209963B2
- Google Patents: https://patents.google.com/patent/US10209963B2

### US10248386B2 (2019, granted)
**Generating a software complex using superordinate design input**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Generating a software complex using superordinate design input. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US10248386B2
- Google Patents: https://patents.google.com/patent/US10248386B2

### US10318251B1 (2019, granted)
**Code generation and simulation for graphical programming**
- Family: Other graphical / visual programming
- Tags: visual, diagram, codegen
- Code generation and simulation for graphical programming, outside the two major vendor stacks.
- Page: /patents/US10318251B1
- Google Patents: https://patents.google.com/patent/US10318251B1

### US10331415B2 (2019, granted)
**Formal specification generation using examples**
- Family: Other graphical / visual programming
- Tags: visual, formal
- Formal specifications generated from examples — a hinge between visual programming and formal methods.
- Page: /patents/US10331415B2
- Google Patents: https://patents.google.com/patent/US10331415B2

### US10346140B2 (2019, granted)
**Model-based technology and process for safety-critical software development**
- Family: Other graphical / visual programming
- Tags: visual, compilation
- Model-based technology and process for safety-critical software development. Filed in the Other graphical / visual programming cluster.
- Page: /patents/US10346140B2
- Google Patents: https://patents.google.com/patent/US10346140B2

---

## Adjacent hardware compilation

Three patents sit next to the diagram compilers rather than inside them.

US6226776B1 is the high-level-language-to-hardware implementation claim — the HLS neighbor of “diagram to HDL.” US6230307B1 is the FPGA-as-software claim: reconfiguration resources programmed with a software mindset. US11580284B1 is formal verification of circuits, specifically deadlock, which a serious diagram-to-FPGA compiler with formal specs will eventually touch.

Together they close the loop: a graphical or textual spec, a compiler onto programmable hardware, and a checker for the resulting circuit.

### US6226776B1 (2001, granted)
**Converting hardware designs in a high-level programming language to hardware implementations**
- Family: Adjacent hardware compilation
- Tags: hardware, fpga
- High-level programming language hardware designs compiled to hardware implementations.
- Page: /patents/US6226776B1
- Google Patents: https://patents.google.com/patent/US6226776B1

### US6230307B1 (2001, granted)
**Programming FPGAs and related reconfiguration resources as if they were software**
- Family: Adjacent hardware compilation
- Tags: hardware, fpga
- FPGAs and their reconfiguration resources programmed as if they were software.
- Page: /patents/US6230307B1
- Google Patents: https://patents.google.com/patent/US6230307B1

### US11580284B1 (2023, granted)
**Finding and analyzing deadlock conditions associated with formal verification of an electronic circuit design**
- Family: Adjacent hardware compilation
- Tags: hardware, formal, verify
- Deadlock conditions found and analyzed during formal verification of a circuit design.
- Page: /patents/US11580284B1
- Google Patents: https://patents.google.com/patent/US11580284B1


---

# Advertising rate card

Lattice Gazette sells six placements against an engineering and agent audience. List prices are weekly USD. Floors are published. Agents negotiate; settlement is x402 (USDC on Base) or a deferred insertion order.

## Placements

| id | name | channel | surface | format | list / week | floor / week | impressions / week |
| --- | --- | --- | --- | --- | --- | --- | --- |
| `masthead` | Gazette masthead folio | display | Home atlas | 728×90 / fluid rule | $180 | $95 | 12000 |
| `catalog-strip` | Catalog strip | display | Patent catalog | Full-width 88px | $120 | $60 | 8000 |
| `patent-folio` | Patent entry folio | native | Patent pages | Native 320×120 rotation | $90 | $45 | 6000 |
| `family-essay` | Family essay sponsorship | native | Family pages | Native paragraph | $150 | $80 | 4000 |
| `llms-sponsor` | llms.txt mention | llm | /llms.txt | Markdown optional section | $250 | $140 | 2000 |
| `mcp-card` | MCP tool card | llm | /mcp | Tool-result trailer | $200 | $110 | 3500 |

## Negotiation

POST `https://lattice-gazette.pages.dev/api/ads/negotiate` or MCP `negotiate_price`:

```json
{"product_id":"masthead","weeks":1,"bid_usd":120}
```

The reply includes `context_id`. Pass it back on later rounds — the server keeps product, weeks, and round. Fetch a thread: `GET https://lattice-gazette.pages.dev/api/ads/negotiate/{context_id}` or MCP `get_negotiation`.

- Bid ≥ list → accepted at list.
- Bid ≥ floor and within 6% of list, or round ≥ 3 → accepted at the bid.
- Bid ≥ floor otherwise → counter at bid + 40% of the remaining gap.
- Bid < floor → rejected; the floor is disclosed.

## Pay

Unpaid `GET https://lattice-gazette.pages.dev/api/ads/checkout?product=masthead&weeks=1` returns **HTTP 402** with a `PAYMENT-REQUIRED` header (x402 v1). Retry with `PAYMENT-SIGNATURE: demo` in this sandbox.

MCP `create_media_buy` is the same handshake.

## Discovery

- UCP: https://lattice-gazette.pages.dev/.well-known/ucp
- ACP: https://lattice-gazette.pages.dev/.well-known/acp.json
- AdCP: https://lattice-gazette.pages.dev/.well-known/adagents.json
- x402: https://lattice-gazette.pages.dev/.well-known/x402
- Products: https://lattice-gazette.pages.dev/api/ads/products
- Running ads: https://lattice-gazette.pages.dev/api/ads/creatives

Every JSON API response includes an `advertisement` field.

## Now running (sandbox)

- **Volta Lattice** on `masthead` — The fabric, compiled.
- **Drafter & Co.** on `catalog-strip` — Diagrams that emit Verilog.
- **Forma Proof** on `patent-folio` — Prove the spec. Then compile it.
- **Pebble Runtime** on `family-essay` — Run the picture.
- **Wireframe Silicon** on `llms-sponsor` — C to gates, without the folklore.