# Lattice Gazette

> Prior art on compiling diagrams into executable specifications for computers and FPGAs.

A public, agent-readable atlas of patents covering graphical programs, formal specifications, and the compilers that lower them onto CPUs and programmable hardware.

- Patents indexed: 89
- Span: 1989–2025
- Families: 6

Read the [landscape essay](https://lattice-gazette.pages.dev/landscape.md), browse [all patents](https://lattice-gazette.pages.dev/patents.md), buy a [placement](https://lattice-gazette.pages.dev/inventory.md), or query the MCP server at `/mcp`.

## Families

### National Instruments / LabVIEW (32)
The densest cluster: virtual instruments as dataflow graphs, then conversion of those graphs into hardware descriptions, probes, resource estimates, and multi-model-of-computation programs.
→ /families/labview.md

### MathWorks / Simulink (19)
Model-based design: block diagrams and state machines compiled to C, HDL, and partitioned targets, with a heavy test-generation and verification overlay.
→ /families/simulink.md

### Formal specification to code (19)
A separate lineage: write a formal (or semi-formal) specification, then synthesize software, UIs, or digital-circuit implementations, often with checking against the spec.
→ /families/formal-spec.md

### UML/SysML to HDL (1)
A thin but distinct bridge: modelling-language code (UML/SysML-class) automatically translated into hardware-language code.
→ /families/uml-hdl.md

### Other graphical / visual programming (15)
Block-diagram simulators, immersive visual programming, evented dataflow, converting visual diagrams into code, signal-processing pipelines, and safety-critical model-based processes.
→ /families/visual.md

### Adjacent hardware compilation (3)
Not always a diagram: C-class hardware designs compiled to gates, FPGAs programmed as if they were software, and deadlock analysis in formally verified circuits.
→ /families/hardware.md